It is estimated that the semiconductor industry currently spends more than one billion U.S. Dollars each year manufacturing silicon wafers that exhibit very flat and smooth surfaces. Typically, chemical mechanical polishing (“CMP”) is used in the manufacturing process of semiconductor devices to obtain smooth and even-surfaced wafers. In a conventional process, a wafer to be polished is generally held by a carrier positioned on a polishing pad attached above a rotating platen. As slurry is applied to the pad and pressure is applied to the carrier, the wafer is polished by relative movement of the platen and the carrier.
While this well-known process has been used successfully for many years, it suffers from a number of problems. For example, this conventional process is relatively expensive and is not always effective, as the silicon wafers may not be uniform in thickness, nor may they be sufficiently smooth, after completion of the process. In addition to becoming overly “wavy” when etched by a solvent, the surface of the silicon wafers may become chipped by individual abrasive grits used in the process. Moreover, if the removal rate is to be accelerated to achieve a higher productivity, the grit size used on the polishing pad must be increased, resulting in a corresponding increase in the risk of scratching or gouging expensive wafers. Furthermore, because surface chipping can be discontinuous, the process throughput can be very low. Consequently, the wafer surface preparation of current state-of-the-art processes is generally expensive and slow.
In addition to these considerations, the line width (e.g., nodes) of the circuitry on semiconductors is now approaching the virus domain (e.g., 10-100 nm). In addition, more layers of circuitry are now being laid down to meet the increasing demands of advanced logic designs. In order to deposit layers for making nanometer sized features, each layer must be extremely flat and smooth during the semiconductor fabrication. While diamond grid pad conditioners have been effectively used in dressing CMP pads for polishing previous designs of integrated circuitry, they have not been found suitable for making cutting-edge devices with nodes smaller than 65 nm. This is because, with the decreasing size of the copper wires, non-uniform thickness due to rough- or over-polishing will change the electrical conductivity dramatically. Moreover, due to the use of coral-like dielectric layers, the fragile structure must be polished very gently to avoid disintegration. Hence, the pressure used in CMP processes must be reduced significantly.
In response, new CMP processes, such as those utilizing electrolysis (e.g. Applied Materials ECMP) of copper or those utilizing air film cushion support of wafer (e.g. Tokyo Semitsu), are being pursued to reduce the polishing pressure on the contact points between wafer and pad. However, as a consequence of gentler polishing action, the polishing rate of the wafer will decrease. To compensate for the loss of productivity, polishing must occur simultaneously over the entire surface of the wafer. In order to do so, the contact points between the wafer and the pad must be smaller in area, but more numerous in frequency. This is in contrast to current CMP practice in which the contacted areas are relatively large but relatively few in number.
Thus, in order to polish fragile wafers more and more gently, the CMP pad asperities must be reduced. However, to prevent the polishing rate from declining, more contact points must be created. Consequently, the pad asperities need to be finer in size but more in number. However, the more delicate the polishing process becomes, the higher the risk of scratching the surface of the wafer becomes. In order to avoid this risk, the highest tips of all asperities must be fully leveled. Otherwise, the protrusion of a few “killer asperities” can ruin the polished wafer.